Cores-SweRV: [https://github.com/chipsallia...]e200_opensource: https://github.com/SI-RISCV/e200_opensourceariane: https://github.com/pulp-platform/arianersd: https://github.com/rsd-devel/rsdultraembedded_riscv: https://github.com/ultraembedded/riscvultraembedded_ipcores: https://github.com/ultraembedded/coresschoolMIPS: https://github.com/MIPSfpga/schoolMIPSpatmos: https://github.com/t-crest/patmosverilog-pcie: https://github.com/alexforencich/verilog-pcieverilog-axi: https://github.com/alexforencich/verilog-axiwb2axi: https://github.com/ZipCPU/wb2axipalice5: https://github.com/bradgrantham/alice5black-parrot: https://github.com/black-parrot/black-parrot

BlackParrot aims to be the default Linux-capable, cache-coherent, RV64GC multicore used by the world.

zet: https://github.com/marmolejo/zet Open source implementation of a x86 processorao486: https://github.com/alfikpl/ao486 The ao486 is an x86 compatible Verilog core implementing all features of a 486 SX.VexRiscv: https://github.com/SpinalHDL/VexRiscv A FPGA friendly 32 bit RISC-V CPU implementation from SpinalHDLhadbadge2019_fpgasoc: FPGA SoC code and application example for Hackaday Supercon 2019 badge

https://github.com/Spritetm/hadbadge2019_fpgasoc

vortexgpgpu Vortex is a full-system RISCV-based GPGPU processor. https://github.com/vortexgpgpu/vortex